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?006 fairchild semiconductor corporation 1 www.fairchildsemi.com HCPL062N rev. 1.0.0 HCPL062N 3.3v dual channel high speed-10 mbit/s logic gate optocouplers tm j uly 2006 HCPL062N 3.3v dual channel high speed-10 mbit/s logic gate optocouplers features compact so8 package ve ry high speed ?10mbit/s superior cmr ?25kv/? minimum (1,000 volts common mode) logic gate output wired or-open collector fixed threshold detector design minimizes thermal impact on switching times u .l. recognized (file # e90700) applications ground loop elimination field buses line receiver, data transmission data multiplexing switching power supplies pulse transformer replacement computer-peripheral interface instrumentation input/output isolation description the HCPL062N optocouplers consist of an algaas led, optically coupled to a very high speed integrated photo- detector logic gate consisting of bipolar transistors on a cmos process for reduced power consumption. the output features an open collector, thereby permitting wired or outputs. the devices are housed in a compact small-outline package. the coupled parameters are guaranteed over the temperature range of -40? to +85?. an internal noise shield and provides superior common mode rejection. pa ck ag e dimensions lead coplanarity : 0.004 (0.10) max 0.202 (5.13) pin 1 0.019 (0.48) 0.182 (4.63) 0.021 (0.53) 0.011 (0.28) 0.050 (1.27) typ 0.244 (6.19) 0.224 (5.69) 0.143 (3.63) 0.123 (3.13) 0.008 (0.20) 0.003 (0.08) 0.010 (0.25) 0.006 (0.16) seati ng plane 0.164 (4.16) 0.144 (3.66) note: all dimensions are in inches (millimeters)
2 www.fairchildsemi.com HCPL062N rev. 1.0.0 HCPL062N 3.3v dual channel high speed-10 mbit/s logic gate optocouplers circuit drawing (1) note: 1. the v cc supply to each optoisolator must be bypassed by a 0.1? capacitor or larger. this can be either a ceramic or solid tantalum capacitor with good high frequency characteristic and should be connected no further than 3mm from the v cc and gnd pins of each device. t ruth table (positive logic) a 0.1? bypass capacitor must be connected between pins 8 and 5. input output hl lh 1 2 3 4 5 6 7 8 + _ v f1 v cc v 01 v 02 gnd v f2 _ +
3 www.fairchildsemi.com HCPL062N rev. 1.0.0 HCPL062N 3.3v dual channel high speed-10 mbit/s logic gate optocouplers absolute maximum ratings (no derating required up to 85?) recommended operating conditions note: 2. 6.3ma is a guard banded value which allows for at least 20% ctr degradation. initial input current threshold value is 5.0ma or less symbol parameter value units t stg storage temperature -40 to +125 ? t opr operating temperature -40 to +85 ? emitter i f dc/average forward input current (each channel) 50 ma v r reverse input voltage (each channel) 5.0 v p i po w er dissipation 45 mw detector v cc (1 minute max) supply voltage 7.0 v i o output current (each channel) 15 ma v o output voltage (each channel) 7.0 v p o collector output power dissipation 85 mw symbol parameter min. max. units i fl input current, low level 0 250 ? i fh input current, high level 6.3 (2) 15 ma v cc supply voltage, output 2.7 3.3 v t a operating temperature -40 +85 ? nf an out (ttl load) 5 ttl loads r l output pull-up 330 4k ?
4 www.fairchildsemi.com HCPL062N rev. 1.0.0 HCPL062N 3.3v dual channel high speed-10 mbit/s logic gate optocouplers electrical characteristics (t a = -40? to +85? unless otherwise speci?d.) individual component characteristics switching characteristics (t a = -40? to +85?, v cc = 3.3v, i f = 7.5 ma unless otherwise speci?d.) symbol parameter test conditions min. typ. (3) max. unit emitter v f input forward voltage i f = 10ma 1.8 v t a =25? 1.75 b vr input reverse breakdown v oltage i r = 10? 5.0 v ? v f / ? t a input diode temperature coef?ient i f = 10ma -1.5 mv/? detector i cch high level supply current i f = 0ma, v cc = 3.3v 7.1 10 ma i ccl low level supply current i f = 10ma, v cc = 3.3v 6.7 15 ma symbol ac characteristics test conditions min. typ. (3) max. unit t plh propagation delay time to output high level r l = 350 ? , c l = 15pf note 4, fig. 10 90 ns t phl propagation delay time to output low level r l = 350 ? , c l = 15pf note 5, fig. 10 75 ns |t phl ? plh | pulse width distortion r l = 350 ? , c l = 15pf fig. 10 25 ns t r output rise time (10?0%) r l = 350 ? , c l = 15pf) note 6, fig. 10 ?6ns t f output fall time (90?0%) r l = 350 ? , c l = 15pf note 7, fig. 10 ?ns |cm h | common mode tr ansient immunity (at output high level) r l = 350 ? , t a = 25?, i f = 0 ma, v cc = 3.3v, v o(min.) = 2v |v cm | = 1,000v notes 8, 11, fig. 11 25,000 v/? |cm l | common mode tr ansient immunity (at output low level) r l = 350 ? , t a =25?, i f = 7.5ma, v cc = 3.3v, v o(max.) = 0.8v |v cm | = 1,000v notes 9, 11, fig. 11 25,000 v/?
5 www.fairchildsemi.com HCPL062N rev. 1.0.0 HCPL062N 3.3v dual channel high speed-10 mbit/s logic gate optocouplers t ransfer characteristics (t a = -40? to +85? unless otherwise speci?d.) isolation characteristics (t a = -40? to +85? unless otherwise speci?d.) notes: 3. all typical values are at v cc = 3.3v, t a = 25? unless otherwise specified. 4. t plh ?propagation delay is measured from the 3.75 ma level on the high to low transition of the input current pulse to the 1.5v level on the low to high transition of the output voltage pulse. 5. t phl ?propagation delay is measured from the 3.75 ma level on the low to high transition of the input current pulse to the 1.5v level on the high to low transition of the output voltage pulse. 6. t r ?rise time is measured from the 90% to the 10% levels on the low to high transition of the output pulse. 7. t f ?fall time is measured from the 10% to the 90% levels on the high to low transition of the output pulse. 8. cm h ?the maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the high state (i.e., v out > 2.0 v). measured in volts per microsecond (v/?). 9. cm l ?the maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in the low output state (i.e., v out < 0.8 v). measured in volts per microsecond (v/?). 10. device considered a two-terminal device: pins 1,2,3 and 4 shorted together, and pins 5,6,7 and 8 shorted together. 11. the power supply bypass capacitors must be no further than 3mm from the leads of the optocoupler. a low inductance ground plane width of with 5nhy of series lead inductance is required. symbol dc characteristics test conditions min. typ. (3) max. unit v ol low level output voltage v cc = 3.3v, i f = 5ma, i ol = 13ma 0.6 v i ft input threshold current v cc = 3.3v, v o = 0.6v, i ol = 13ma 5 ma symbol characteristics test conditions min. typ. (3) max. unit i i-o input-output insulation leakage current relative humidity = 45% t a = 25?, t = 5 sec. v i-o = 3000 vdc, note 10 1.0 ? v iso withstand insulation test v oltage r h < 50%, t a = 25? i i-o 2?, t = 1 min., note 10 2500 v rms r i-o resistance (input to output) v i-o = 500v, note 10 10 12 ? c i-o capacitance (input to output) f = 1mhz, note 10 0.6 pf
6 www.fairchildsemi.com HCPL062N rev. 1.0.0 HCPL062N 3.3v dual channel high speed-10 mbit/s logic gate optocouplers t ypical performance curves fig. 1 forward current vs. forward voltage v f ?forward voltage (v) i f ?forward current (ma) fig. 2 high level output current vs. ambient temperature i th - input threshold current (ma) i ol - low level output current (ma) fig. 3 low level output current vs. ambient temperature t a ?ambient temperature ( c) t a ?ambient temperature ( c) fig. 4 input threshold current vs. temperature t a ?ambient temperature ( c) i oh ?high level output current (na) -40 -20 0 20 4 06080100 -40 -20 0 20 4 06080100 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 0.001 0.01 0.1 1 10 100 t a = 100 o c t a = 85 o c t a = -40 o c t a = 0 o c t a = 25 o c -40 -20 0 20 40 60 80 100 0 2 4 6 8 10 12 v o = v cc = 3.3v i f = 250 a 0.0 0.5 1.0 1.5 2.0 2.5 v cc = 3.3v v o = 0.6v r l = 350 ? , 1k ? , 4k ? 10 15 20 25 30 35 40 v cc = 3.3v v ol = 0.6v i f = 5ma
7 www.fairchildsemi.com HCPL062N rev. 1.0.0 HCPL062N 3.3v dual channel high speed-10 mbit/s logic gate optocouplers t ypical performance curves (continued) fig. 5 pulse width distortion vs. ambient temperature t a ?ambient temperature (?c) t a ?ambient temperature (?c) pwd ? pulse width distortion (ns) t p ?propagation delay (ns) fig. 6 propagation delay vs. pulse input current t r , t f ?rise, fall times (ns) fig. 7 propagation delay vs. ambient temperature fig. 8 rise and fall times vs. ambient temperature -40 -20 0 20 4 06080100 -40 -20 0 20 4 06080100 0 5 10 15 20 25 30 v cc = 3.3v i f = 7.5ma r l = 350 ? 100 90 80 70 60 50 40 30 20 v cc = 3.3v i f = 7.5ma t phl r l = 350 ? t plh t a ?ambient temperature (?c) -40 -20 0 20 4 06080100 30 25 20 15 10 5 0 v cc = 3.3v i f = 7.5ma t f r l = 350 ? t r i f ?pulse input current (ma) t p ?propagation delay (ns) 57911 13 15 0 20 40 60 80 100 120 v cc = 3.3v t a = 25 o c t phl t plh r l = 350 ?
8 www.fairchildsemi.com HCPL062N rev. 1.0.0 HCPL062N 3.3v dual channel high speed-10 mbit/s logic gate optocouplers t ypical performance curves (continued) fig. 9 low level output voltage vs. ambient temperature t a ?ambient temperature (?c) v ol ?low level output voltage (v) -4 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0-20 0 20 4 06080100 v cc = 3.3v i o = 13ma i f = 5ma
9 www.fairchildsemi.com HCPL062N rev. 1.0.0 HCPL062N 3.3v dual channel high speed-10 mbit/s logic gate optocouplers t est circuits peak cm v 0v o v 3.3v switching pos. (a), i = 0 f o v (max) cm 0.5 v o v switching pos. (b), i = 7.5 ma f h cm l v (min) o 1 2 3 4 8 b a 7 6 5 dual channel +3.3v i f v cc v cm pulse generator z o = 50 ? +? r l v ff output v o monitoring node 0.1 f bypass gnd fig. 11 test circuit and waveforms for common mode transient immunity 3mm spacing phl t f i = 7.5 ma 1.5 v 90% 10% plh t i = 3.75 ma f out put o (v ) input (i ) f out put (v ) o f t r t fig. 10 test circuit and waveforms for t plh , t phl, t r and t f 1 2 3 4 8 7 6 5 dual channel 3mm spacing pulse gen. z o = 50 ? t f = t r = 5 ns +3.3v i f v cc r m r l input monitoring node output v o monitoring node 0.1 f bypass c l * gnd
10 www.fairchildsemi.com HCPL062N rev. 1.0.0 HCPL062N 3.3v dual channel high speed-10 mbit/s logic gate optocouplers footprint 8-pin small outline 0.024 (0.61) 0.050 (1.27) 0.155 (3.94) 0.275 (6.99) 0.060 (1.52)
11 www.fairchildsemi.com HCPL062N rev. 1.0.0 HCPL062N 3.3v dual channel high speed-10 mbit/s logic gate optocouplers ordering information marking information option order entry identi?er description no suf? HCPL062N shipped in tubes (50 units per tube) r1 HCPL062Nr1 tape and reel (500 units per reel) r2 HCPL062Nr2 tape and reel (2500 units per reel) 1 2 5 3 4 de?nitions 1f airchild logo 2d e vice number 3 one digit year code, e.g., ? 4t wo digit work week ranging from ?1 to ?3 5 assembly package code 62n s yy x
12 www.fairchildsemi.com HCPL062N rev. 1.0.0 HCPL062N 3.3v dual channel high speed-10 mbit/s logic gate optocouplers carrier tape speci?cation re?ow pro?le 4.0 0.10 1.5 min user direction of feed 2.0 0.05 1.75 0.10 5.5 0.05 12.0 0.3 8.0 0.10 0.30 max 8.3 0.10 3.50 0.20 0.1 max 6.40 0.20 5.20 0.20 1.5 0.1/-0 300 280 260 240 220 200 180 160 140 120 100 80 60 40 20 0 c time (s) 0 60 180 120 270 260 c >245 c = 42 sec time above 183 c = 90 sec 360 1.822 c/sec ramp up rate 33 sec
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